1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly to an improved technique suitable for ULSIs of the packing density ranging from 16 M bits to 16 G bits.
2. Description of the Prior Art
An example of MIS FETs associated with capacitances is shown in FIG. 1(A) to form one bit storage element of a semiconductor memory device. A semiconductor substrate 1 is partitioned by a field insulating film 3 into a number of active regions, only one of which is illustrated in the figure. An FET 10 formed within the active region of the substrate 1 comprises lightly doped source and drain regions 4 and 5 flanked respectively with heavily doped impurity regions 14 and 15 for facilitating formation of ohmic contact, a gate electrode 18 insulated from a channel region located between the source and the drain regions 4 and 5 by means of an insulating film 2. A capacitor 20 comprises an impurity semiconductor region 21 functioning as a first electrode and a polysilicon film 23 functioning as a second electrode insulated from the first electrode 21 by an intervening dielectric film 22. Numerals 38 and 38' in the figure designate shoulder portions 38 and 38' provided for the purpose of formation of the source and the drain regions 4 and 5 in such a dual structure. The corresponding circuit diagram of this structure is shown in FIG. 1(B), which constitutes a unit memory cell of 1Tr/Cell DRAM.
Since the unit structure of this prior art is constructed in a one-dimmensional geometry, there is a limitation upon the packing density of the integration. More simple and effective structure is required for increasing the packing density.